1. Field of Invention
This invention relates generally to a central processing unit of a microprocessor and specifically to a bus system within such a central processing unit.
2. Description of Related Art
In a typical microprocessor based computer system, module units within the central processing unit (CPU) such as, for instance, instruction caches, data caches, a DRAM memory controller, a Peripheral Component Interconnect (PCI) interface unit, and so on, communicate with one another via a common bus. Typically, each of the module units communicates with the common bus through a tri-state I/O driver which, in turn, is controlled by a central bus controller. Since the common bus handles only one transaction at a time, a bus control system is necessary to arbitrate control of the common bus to the module units in a manner which optimizes CPU performance. See, for instance, U.S. Pat. No. 5,590,380 to Yamada et al and U.S. Pat. No. 5,528,767 to Chen. In some bus control and arbitration systems, bus control is granted to a particular module unit until the present transaction is completed. In other systems, bus control is granted for a predetermined period of time, regardless of whether the present transaction is completed. Most conventional bus control and arbitration systems have an interrupt feature whereby bus control is immediately granted to a specific unit such as, for instance, the memory controller when it is desired to receive streamline audio video information from an external source, e.g., the Internet.
Unfortunately, conventional bus control and arbitration systems undesirably limit CPU performance. For instance, the transmission and reception of data to and from each module unit during a transaction is controlled by the tri-state I/O drivers within the module units. The tri-state drivers, in turn, are controlled by the central bus controller. Thus, when a transaction requires data and control signals to be sent back and forth between two module units, the tri-state drivers within these two module units must first alert the central bus controller which, in response thereto, provides control signals back to the tri-state drivers. This command hierarchy consumes an undesirable amount of time and, therefore, undesirably limits CPU performance. In addition, the time required to switch the tri-state drivers between states consumes time and, thus, further limits CPU performance. CPU performance is further limited by the time required to arbitrate among present transaction requests.